Dmitry Shalnoff's Git Repository - LightSticks/blob - HARDWARE/lightsticks_extender.pro

   1 update=Sun 10 Nov 2019 04:07:14 PM CET
   2 version=1
   3 last_client=kicad
   4 [general]
   5 version=1
   6 RootSch=
   7 BoardNm=
   8 [cvpcb]
   9 version=1
  10 NetIExt=net
  11 [eeschema]
  12 version=1
  13 LibDir=
  14 [eeschema/libraries]
  15 [schematic_editor]
  16 version=1
  17 PageLayoutDescrFile=
  18 PlotDirectoryName=
  19 SubpartIdSeparator=0
  20 SubpartFirstId=65
  21 NetFmtName=Pcbnew
  22 SpiceAjustPassiveValues=0
  23 LabSize=50
  24 ERC_TestSimilarLabels=1
  25 [pcbnew]
  26 version=1
  27 PageLayoutDescrFile=
  28 LastNetListRead=lightsticks_extender.net
  29 CopperLayerCount=2
  30 BoardThickness=1.6
  31 AllowMicroVias=0
  32 AllowBlindVias=0
  33 RequireCourtyardDefinitions=0
  34 ProhibitOverlappingCourtyards=1
  35 MinTrackWidth=0.2
  36 MinViaDiameter=0.4
  37 MinViaDrill=0.3
  38 MinMicroViaDiameter=0.2
  39 MinMicroViaDrill=0.09999999999999999
  40 MinHoleToHole=0.25
  41 TrackWidth1=0.25
  42 TrackWidth2=0.5
  43 ViaDiameter1=0.8
  44 ViaDrill1=0.4
  45 ViaDiameter2=0.8
  46 ViaDrill2=0.4
  47 dPairWidth1=0.2
  48 dPairGap1=0.25
  49 dPairViaGap1=0.25
  50 SilkLineWidth=0.12
  51 SilkTextSizeV=1
  52 SilkTextSizeH=1
  53 SilkTextSizeThickness=0.15
  54 SilkTextItalic=0
  55 SilkTextUpright=1
  56 CopperLineWidth=0.2
  57 CopperTextSizeV=1.5
  58 CopperTextSizeH=1.5
  59 CopperTextThickness=0.3
  60 CopperTextItalic=0
  61 CopperTextUpright=1
  62 EdgeCutLineWidth=0.05
  63 CourtyardLineWidth=0.05
  64 OthersLineWidth=0.15
  65 OthersTextSizeV=1
  66 OthersTextSizeH=1
  67 OthersTextSizeThickness=0.15
  68 OthersTextItalic=0
  69 OthersTextUpright=1
  70 SolderMaskClearance=0.051
  71 SolderMaskMinWidth=0.25
  72 SolderPasteClearance=0
  73 SolderPasteRatio=-0
  74 [pcbnew/Layer.F.Cu]
  75 Name=F.Cu
  76 Type=0
  77 Enabled=1
  78 [pcbnew/Layer.In1.Cu]
  79 Name=In1.Cu
  80 Type=0
  81 Enabled=0
  82 [pcbnew/Layer.In2.Cu]
  83 Name=In2.Cu
  84 Type=0
  85 Enabled=0
  86 [pcbnew/Layer.In3.Cu]
  87 Name=In3.Cu
  88 Type=0
  89 Enabled=0
  90 [pcbnew/Layer.In4.Cu]
  91 Name=In4.Cu
  92 Type=0
  93 Enabled=0
  94 [pcbnew/Layer.In5.Cu]
  95 Name=In5.Cu
  96 Type=0
  97 Enabled=0
  98 [pcbnew/Layer.In6.Cu]
  99 Name=In6.Cu
 100 Type=0
 101 Enabled=0
 102 [pcbnew/Layer.In7.Cu]
 103 Name=In7.Cu
 104 Type=0
 105 Enabled=0
 106 [pcbnew/Layer.In8.Cu]
 107 Name=In8.Cu
 108 Type=0
 109 Enabled=0
 110 [pcbnew/Layer.In9.Cu]
 111 Name=In9.Cu
 112 Type=0
 113 Enabled=0
 114 [pcbnew/Layer.In10.Cu]
 115 Name=In10.Cu
 116 Type=0
 117 Enabled=0
 118 [pcbnew/Layer.In11.Cu]
 119 Name=In11.Cu
 120 Type=0
 121 Enabled=0
 122 [pcbnew/Layer.In12.Cu]
 123 Name=In12.Cu
 124 Type=0
 125 Enabled=0
 126 [pcbnew/Layer.In13.Cu]
 127 Name=In13.Cu
 128 Type=0
 129 Enabled=0
 130 [pcbnew/Layer.In14.Cu]
 131 Name=In14.Cu
 132 Type=0
 133 Enabled=0
 134 [pcbnew/Layer.In15.Cu]
 135 Name=In15.Cu
 136 Type=0
 137 Enabled=0
 138 [pcbnew/Layer.In16.Cu]
 139 Name=In16.Cu
 140 Type=0
 141 Enabled=0
 142 [pcbnew/Layer.In17.Cu]
 143 Name=In17.Cu
 144 Type=0
 145 Enabled=0
 146 [pcbnew/Layer.In18.Cu]
 147 Name=In18.Cu
 148 Type=0
 149 Enabled=0
 150 [pcbnew/Layer.In19.Cu]
 151 Name=In19.Cu
 152 Type=0
 153 Enabled=0
 154 [pcbnew/Layer.In20.Cu]
 155 Name=In20.Cu
 156 Type=0
 157 Enabled=0
 158 [pcbnew/Layer.In21.Cu]
 159 Name=In21.Cu
 160 Type=0
 161 Enabled=0
 162 [pcbnew/Layer.In22.Cu]
 163 Name=In22.Cu
 164 Type=0
 165 Enabled=0
 166 [pcbnew/Layer.In23.Cu]
 167 Name=In23.Cu
 168 Type=0
 169 Enabled=0
 170 [pcbnew/Layer.In24.Cu]
 171 Name=In24.Cu
 172 Type=0
 173 Enabled=0
 174 [pcbnew/Layer.In25.Cu]
 175 Name=In25.Cu
 176 Type=0
 177 Enabled=0
 178 [pcbnew/Layer.In26.Cu]
 179 Name=In26.Cu
 180 Type=0
 181 Enabled=0
 182 [pcbnew/Layer.In27.Cu]
 183 Name=In27.Cu
 184 Type=0
 185 Enabled=0
 186 [pcbnew/Layer.In28.Cu]
 187 Name=In28.Cu
 188 Type=0
 189 Enabled=0
 190 [pcbnew/Layer.In29.Cu]
 191 Name=In29.Cu
 192 Type=0
 193 Enabled=0
 194 [pcbnew/Layer.In30.Cu]
 195 Name=In30.Cu
 196 Type=0
 197 Enabled=0
 198 [pcbnew/Layer.B.Cu]
 199 Name=B.Cu
 200 Type=0
 201 Enabled=1
 202 [pcbnew/Layer.B.Adhes]
 203 Enabled=1
 204 [pcbnew/Layer.F.Adhes]
 205 Enabled=1
 206 [pcbnew/Layer.B.Paste]
 207 Enabled=1
 208 [pcbnew/Layer.F.Paste]
 209 Enabled=1
 210 [pcbnew/Layer.B.SilkS]
 211 Enabled=1
 212 [pcbnew/Layer.F.SilkS]
 213 Enabled=1
 214 [pcbnew/Layer.B.Mask]
 215 Enabled=1
 216 [pcbnew/Layer.F.Mask]
 217 Enabled=1
 218 [pcbnew/Layer.Dwgs.User]
 219 Enabled=1
 220 [pcbnew/Layer.Cmts.User]
 221 Enabled=1
 222 [pcbnew/Layer.Eco1.User]
 223 Enabled=1
 224 [pcbnew/Layer.Eco2.User]
 225 Enabled=1
 226 [pcbnew/Layer.Edge.Cuts]
 227 Enabled=1
 228 [pcbnew/Layer.Margin]
 229 Enabled=1
 230 [pcbnew/Layer.B.CrtYd]
 231 Enabled=1
 232 [pcbnew/Layer.F.CrtYd]
 233 Enabled=1
 234 [pcbnew/Layer.B.Fab]
 235 Enabled=1
 236 [pcbnew/Layer.F.Fab]
 237 Enabled=1
 238 [pcbnew/Layer.Rescue]
 239 Enabled=0
 240 [pcbnew/Netclasses]
 241 [pcbnew/Netclasses/Default]
 242 Name=Default
 243 Clearance=0.2
 244 TrackWidth=0.25
 245 ViaDiameter=0.8
 246 ViaDrill=0.4
 247 uViaDiameter=0.3
 248 uViaDrill=0.1
 249 dPairWidth=0.2
 250 dPairGap=0.25
 251 dPairViaGap=0.25